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Ethernet and MII management
The following figure shows the RMII transmit AC timing diagram.
REF_CLK
t RMXH
t RMX
t RMXF
t RMXR
TXD[1:0]
TX_EN
t RMTKHDX
Figure 15. RMII transmit AC timing diagram
8.2.2.2
RMII receive AC timing specifications
The following table provides the RMII receive AC timing specifications.
Table 23. RMII receive AC timing specifications
At recommended operating conditions with OV DD of 3.3 V ± 300mV.
Parameter/Condition
REF_CLK clock period
REF_CLK duty cycle
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
REF_CLK clock rise V IL (min) to V IH (max)
REF_CLK clock fall time V IH (max) to V IL (min)
Symbol 1
t RMX
t RMXH /t RMX
t RMRDVKH
t RMRDXKH
t RMXR
t RMXF
Min
—
35
4.0
2.0
1.0
1.0
Typical
20
—
—
—
—
—
Max
—
65
—
—
4.0
4.0
Unit
ns
%
ns
ns
ns
ns
Note:
1. The symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t RMRDVKH symbolizes RMII
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the t RMX clock
reference (K) going to the high (H) state or setup time. Also, t RMRDXKL symbolizes RMII receive timing (RMR) with respect to
the time data input signals (D) went invalid (X) relative to the t RMX clock reference (K) going to the low (L) state or hold time.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t RMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
26
Freescale Semiconductor
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